Data storage devices can be used to store and retrieve user data in a fast and effective manner. Some data storage devices utilize a semiconductor array of solid-state memory cells to store data. The memory cells can be volatile or non-volatile. Some non-volatile memory cells can be provided with a 1T1R configuration with a single transistor (“T”) and a single programmable resistive sense element (“R”).
The resistive sense element is programmable to different resistive states through the application of write currents to the memory cell, and these different resistive states can be used to denote different logical states (e.g., logical 0, 1, 10, etc.). The programmed state of the resistive sense element can be sensed using a sense amplifier to detect a voltage generated by passage of a read current through the memory cell. A number of resistive sense element (RSE) constructions are known, including without limitation magnetic random access memory (MRAM), spin-torque transfer random access memory (STRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), and programmable metallic cells (PMCs).
The memory cell transistor serves as a switching device to facilitate access to the memory cell during write and read operations, and to decouple the memory cell from adjacent cells at other times. The cell transistor may be realized as an n-channel metal oxide semiconductor field effect transistor (NMOSFET).
The cell transistor will be sized to accommodate the relatively large bi-directional write currents used to program the RSE to different resistive states, and can require a substantially greater semiconductor area than the associated RSE in the cell. The size of the cell transistor can thus serve as a limiting factor in achieving greater areal data storage densities in a semiconductor array.